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LT3500
8
3500fc
PIN FUNCTIONS
Driving the R
T
/SYNC pin with an external clock signal
will synchronize the switch to the applied frequency.
Synchronization occurs on the rising edge of the clock
signal after the clock signal is detected. Each rising clock
edge initiates an oscillator ramp reset. A gain control loop
servos the oscillator charging current to maintain a con-
stant oscillator amplitude. Hence, the slope compensation
remains unchanged. If the clock signal is removed, the
oscillator reverts to resistor mode and reapplies the 1V
bias to the R
T
/SYNC pin after the synchronization detection
circuitry times out. The clock source impedance should
be set such that the current out of the R
T
/SYNC pin in
resistor mode generates a frequency roughly equivalent
to the synchronization frequency. Floating or holding the
R
T
/SYNC pin above 1.1V will not damage the device, but
will halt oscillation.
PG: The power good bar pin is an open-collector output 
that sinks current when the FB or LFB rises above 90%
of its nominal regulating voltage.
FB: The FB pin is the negative input to the switcher error 
ampli er. The output switches to regulate this pin to 0.8V
with respect to the exposed ground pad. Bias current
 ows out of the FB pin.
LFB: The LFB pin is the negative input to the linear error 
ampli er. The L
DRV
 pin servos to regulate this pin to 0.8V
with respect to the exposed ground pad. Bias current  ows
out of the LFB pin.
LDRV: The LDRV pin is the emitter of an internal NPN that 
can be con gured as an output of a linear regulator or as
the drive for an external NPN high current regulator. Cur-
rent  ows out of the LDRV pin when the LFB pin voltage is
below 0.8V. The LDRV pin has a typical maximum current
capability of 13mA.
BST: The BST pin provides a higher than V
IN
 base drive to
the power NPN to ensure a low switch drop. A compara-
tor to V
IN
 imposes a minimum off time on the SW pin if
the BST pin voltage drops too low. Forcing a SW off time
allows the boost capacitor to recharge.
SW: The SW pin is the emitter of the on-chip power NPN. 
At switch off, the inductor will drive this pin below ground
with a high dV/dt. An external catch diode to ground, close
to the SW pin and respective V
IN
 decoupling capacitors
ground, must be used to prevent this pin from excessive
negative voltages.
Exposed Pad: GND. The exposed pad is the only ground 
connection for the device. The exposed pad should be
soldered to a large copper area to reduce thermal resis-
tance. The GND pin also serves as small-signal ground.
For ideal operation all small-signal ground paths should
connect to the GND pin at a single point, avoiding any
high current ground returns.
NC Pins (MSE Package Only): No Connection. The NC pins 
are electrically isolated from the LT3500. The NC pins may
be connected to PCB traces to aid PCB layout.
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